forked from cory/tildefriends
296 lines
12 KiB
Groff
296 lines
12 KiB
Groff
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.\" ========================================================================
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.\"
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.IX Title "OPENSSL_IA32CAP 3"
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.TH OPENSSL_IA32CAP 3 "2020-04-21" "1.1.1g" "OpenSSL"
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.\" For nroff, turn off justification. Always turn off hyphenation; it makes
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.\" way too many mistakes in technical documents.
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.if n .ad l
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.nh
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.SH "NAME"
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OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
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.SH "SYNOPSIS"
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.IX Header "SYNOPSIS"
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.Vb 1
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\& env OPENSSL_ia32cap=... <application>
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.Ve
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.SH "DESCRIPTION"
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.IX Header "DESCRIPTION"
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OpenSSL supports a range of x86[_64] instruction set extensions. These
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extensions are denoted by individual bits in capability vector returned
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by processor in \s-1EDX:ECX\s0 register pair after executing \s-1CPUID\s0 instruction
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with EAX=1 input value (see Intel Application Note #241618). This vector
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is copied to memory upon toolkit initialization and used to choose
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between different code paths to provide optimal performance across wide
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range of processors. For the moment of this writing following bits are
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significant:
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.IP "bit #4 denoting presence of Time-Stamp Counter." 4
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.IX Item "bit #4 denoting presence of Time-Stamp Counter."
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.PD 0
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.IP "bit #19 denoting availability of \s-1CLFLUSH\s0 instruction;" 4
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.IX Item "bit #19 denoting availability of CLFLUSH instruction;"
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.IP "bit #20, reserved by Intel, is used to choose among \s-1RC4\s0 code paths;" 4
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.IX Item "bit #20, reserved by Intel, is used to choose among RC4 code paths;"
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.IP "bit #23 denoting \s-1MMX\s0 support;" 4
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.IX Item "bit #23 denoting MMX support;"
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.IP "bit #24, \s-1FXSR\s0 bit, denoting availability of \s-1XMM\s0 registers;" 4
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.IX Item "bit #24, FXSR bit, denoting availability of XMM registers;"
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.IP "bit #25 denoting \s-1SSE\s0 support;" 4
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.IX Item "bit #25 denoting SSE support;"
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.IP "bit #26 denoting \s-1SSE2\s0 support;" 4
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.IX Item "bit #26 denoting SSE2 support;"
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.IP "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;" 4
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.IX Item "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;"
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.IP "bit #30, reserved by Intel, denotes specifically Intel CPUs;" 4
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.IX Item "bit #30, reserved by Intel, denotes specifically Intel CPUs;"
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.IP "bit #33 denoting availability of \s-1PCLMULQDQ\s0 instruction;" 4
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.IX Item "bit #33 denoting availability of PCLMULQDQ instruction;"
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.IP "bit #41 denoting \s-1SSSE3,\s0 Supplemental \s-1SSE3,\s0 support;" 4
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.IX Item "bit #41 denoting SSSE3, Supplemental SSE3, support;"
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.IP "bit #43 denoting \s-1AMD XOP\s0 support (forced to zero on non-AMD CPUs);" 4
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.IX Item "bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);"
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.IP "bit #54 denoting availability of \s-1MOVBE\s0 instruction;" 4
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.IX Item "bit #54 denoting availability of MOVBE instruction;"
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.IP "bit #57 denoting AES-NI instruction set extension;" 4
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.IX Item "bit #57 denoting AES-NI instruction set extension;"
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.IP "bit #58, \s-1XSAVE\s0 bit, lack of which in combination with \s-1MOVBE\s0 is used to identify Atom Silvermont core;" 4
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.IX Item "bit #58, XSAVE bit, lack of which in combination with MOVBE is used to identify Atom Silvermont core;"
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.IP "bit #59, \s-1OSXSAVE\s0 bit, denoting availability of \s-1YMM\s0 registers;" 4
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.IX Item "bit #59, OSXSAVE bit, denoting availability of YMM registers;"
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.IP "bit #60 denoting \s-1AVX\s0 extension;" 4
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.IX Item "bit #60 denoting AVX extension;"
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.IP "bit #62 denoting availability of \s-1RDRAND\s0 instruction;" 4
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.IX Item "bit #62 denoting availability of RDRAND instruction;"
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.PD
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.PP
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For example, in 32\-bit application context clearing bit #26 at run-time
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disables high-performance \s-1SSE2\s0 code present in the crypto library, while
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clearing bit #24 disables \s-1SSE2\s0 code operating on 128\-bit \s-1XMM\s0 register
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bank. You might have to do the latter if target OpenSSL application is
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executed on \s-1SSE2\s0 capable \s-1CPU,\s0 but under control of \s-1OS\s0 that does not
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enable \s-1XMM\s0 registers. Historically address of the capability vector copy
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was exposed to application through \fBOPENSSL_ia32cap_loc()\fR, but not
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anymore. Now the only way to affect the capability detection is to set
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OPENSSL_ia32cap environment variable prior target application start. To
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give a specific example, on Intel P4 processor 'env
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OPENSSL_ia32cap=0x16980010 apps/openssl', or better yet 'env
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OPENSSL_ia32cap=~0x1000000 apps/openssl' would achieve the desired
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effect. Alternatively you can reconfigure the toolkit with no\-sse2
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option and recompile.
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.PP
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Less intuitive is clearing bit #28, or ~0x10000000 in the \*(L"environment
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variable\*(R" terms. The truth is that it's not copied from \s-1CPUID\s0 output
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verbatim, but is adjusted to reflect whether or not the data cache is
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actually shared between logical cores. This in turn affects the decision
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on whether or not expensive countermeasures against cache-timing attacks
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are applied, most notably in \s-1AES\s0 assembler module.
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.PP
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The capability vector is further extended with \s-1EBX\s0 value returned by
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\&\s-1CPUID\s0 with EAX=7 and ECX=0 as input. Following bits are significant:
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.IP "bit #64+3 denoting availability of \s-1BMI1\s0 instructions, e.g. \s-1ANDN\s0;" 4
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.IX Item "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;"
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.PD 0
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.IP "bit #64+5 denoting availability of \s-1AVX2\s0 instructions;" 4
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.IX Item "bit #64+5 denoting availability of AVX2 instructions;"
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.IP "bit #64+8 denoting availability of \s-1BMI2\s0 instructions, e.g. \s-1MULX\s0 and \s-1RORX\s0;" 4
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.IX Item "bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and RORX;"
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.IP "bit #64+16 denoting availability of \s-1AVX512F\s0 extension;" 4
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.IX Item "bit #64+16 denoting availability of AVX512F extension;"
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.IP "bit #64+18 denoting availability of \s-1RDSEED\s0 instruction;" 4
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.IX Item "bit #64+18 denoting availability of RDSEED instruction;"
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.IP "bit #64+19 denoting availability of \s-1ADCX\s0 and \s-1ADOX\s0 instructions;" 4
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.IX Item "bit #64+19 denoting availability of ADCX and ADOX instructions;"
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.IP "bit #64+21 denoting availability of VPMADD52[\s-1LH\s0]UQ instructions, a.k.a. \s-1AVX512IFMA\s0 extension;" 4
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.IX Item "bit #64+21 denoting availability of VPMADD52[LH]UQ instructions, a.k.a. AVX512IFMA extension;"
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.IP "bit #64+29 denoting availability of \s-1SHA\s0 extension;" 4
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.IX Item "bit #64+29 denoting availability of SHA extension;"
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.IP "bit #64+30 denoting availability of \s-1AVX512BW\s0 extension;" 4
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.IX Item "bit #64+30 denoting availability of AVX512BW extension;"
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.IP "bit #64+31 denoting availability of \s-1AVX512VL\s0 extension;" 4
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.IX Item "bit #64+31 denoting availability of AVX512VL extension;"
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.IP "bit #64+41 denoting availability of \s-1VAES\s0 extension;" 4
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.IX Item "bit #64+41 denoting availability of VAES extension;"
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.IP "bit #64+42 denoting availability of \s-1VPCLMULQDQ\s0 extension;" 4
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.IX Item "bit #64+42 denoting availability of VPCLMULQDQ extension;"
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.PD
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.PP
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To control this extended capability word use ':' as delimiter when
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setting up OPENSSL_ia32cap environment variable. For example assigning
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\&':~0x20' would disable \s-1AVX2\s0 code paths, and ':0' \- all post-AVX
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extensions.
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.PP
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It should be noted that whether or not some of the most \*(L"fancy\*(R"
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extension code paths are actually assembled depends on current assembler
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version. Base minimum of \s-1AES\-NI/PCLMULQDQ, SSSE3\s0 and \s-1SHA\s0 extension code
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paths are always assembled. Apart from that, minimum assembler version
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requirements are summarized in below table:
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.PP
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.Vb 8
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\& Extension | GNU as | nasm | llvm
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\& \-\-\-\-\-\-\-\-\-\-\-\-+\-\-\-\-\-\-\-\-+\-\-\-\-\-\-\-\-+\-\-\-\-\-\-\-\-
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\& AVX | 2.19 | 2.09 | 3.0
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\& AVX2 | 2.22 | 2.10 | 3.1
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\& ADCX/ADOX | 2.23 | 2.10 | 3.3
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\& AVX512 | 2.25 | 2.11.8 | see NOTES
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\& AVX512IFMA | 2.26 | 2.11.8 | see NOTES
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\& VAES | 2.30 | 2.13.3 |
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.Ve
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.SH "NOTES"
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.IX Header "NOTES"
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Even though \s-1AVX512\s0 support was implemented in llvm 3.6, compilation of
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assembly modules apparently requires explicit \-march flag. But then
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compiler generates processor-specific code, which in turn contradicts
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the mere idea of run-time switch execution facilitated by the variable
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in question. Till the limitation is lifted, it's possible to work around
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the problem by making build procedure use following script:
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.PP
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.Vb 2
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\& #!/bin/sh
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\& exec clang \-no\-integrated\-as "$@"
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.Ve
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.PP
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instead of real clang. In which case it doesn't matter which clang
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version is used, as it is \s-1GNU\s0 assembler version that will be checked.
|
||
|
|
.SH "RETURN VALUES"
|
||
|
|
.IX Header "RETURN VALUES"
|
||
|
|
Not available.
|
||
|
|
.SH "COPYRIGHT"
|
||
|
|
.IX Header "COPYRIGHT"
|
||
|
|
Copyright 2004\-2018 The OpenSSL Project Authors. All Rights Reserved.
|
||
|
|
.PP
|
||
|
|
Licensed under the OpenSSL license (the \*(L"License\*(R"). You may not use
|
||
|
|
this file except in compliance with the License. You can obtain a copy
|
||
|
|
in the file \s-1LICENSE\s0 in the source distribution or at
|
||
|
|
<https://www.openssl.org/source/license.html>.
|